Self-passivated nitrogen-polar iii-nitride transistor

ABSTRACT

A HEMT comprising a channel layer of a first III-Nitride semiconductor material, grown on a N-polar surface of a back barrier layer of a second III-Nitride semiconductor material; the second III-Nitride semiconductor material having a larger band gap than the first III-Nitride semiconductor material, such that a positively charged polarization interface and two-dimensional electron gas is obtained in the channel layer; a passivation, capping layer, of said first III-Nitride semiconductor material, formed on top of and in contact with a first portion of a N-polar surface of said channel layer; a gate trench traversing the passivation, capping layer, and ending at said N-polar surface of said channel layer; and a gate conductor filling said gate trench.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority to, and the benefit of, U.S.Provisional Patent Application No. 63/071,912, filed Aug. 28, 2020, andentitled “Self-Passivated Nitrogen-Polar III-Nitride Transistor.

TECHNICAL FIELD

Embodiments of the present disclosure relate to High Electron MobilityTransistors made on the N-polar surface of a III-Nitride semiconductor,as well as methods of manufacturing thereof.

BACKGROUND

III-Nitride HEMTs, in particular GaN HEMTs, are being increasinglyimplemented in monolithic microwave integrated circuit (MMIC) amplifiersdue to an outstanding combination of properties such as speed, outputpower, and efficiency for transmit applications, and linearity, noisefigure, and RF input survivability for receive applications. Such HEMTscan be used in high-frequency and high-power applications such as:broadband transmitters for electronic warfare jamming, phased arrayradars, Ka-band missile seekers, satellite communication groundterminals, high-power devices for cellular base station applications,and high-voltage devices for switching applications. The vast majorityof GaN HEMTs is reported to-date have utilized a base semiconductorcrystal in the [0001], or gallium-polar (Ga-polar), crystallographicorientation. However, recent reports of [000-1]-oriented GaNHEMTs—so-called “N-polar” GaN—have shown tremendous potential forhigh-power, high-frequency RF performance. In particular, N-polar GaNHEMTs with recessed gates and GaN cap layers have produced record outputpower at millimeter-wave frequencies. See for example Wienecke, Steven,et al. “N-polar GaN cap MISHEMT with record power density exceeding 6.5W/mm at 94 GHz.” IEEE Electron Device Letters 38.3 (2017): 359-362; andRomanczyk, Brian, et al. “Demonstration of constant 8 W/mm power densityat 10, 30, and 94 GHz in state-of-the-art millimeter-wave N-polar GaNMISHEMTs.” IEEE Transactions on Electron Devices 65.1 (2017): 45-50; andalso Guidry, Matthew, et al. “Demonstration of 30 GHz OIP3/PDC 10 dB bymm-Wave N-polar Deep Recess MISHEMTs”. University of California SantaBarbara United States, 2019.

High-frequency N-polar AlxGa1-xN/GaN HEMTs known from the abovereferences have a GaN channel layer formed on the N-polar surface of anAlxGa1-xN barrier layer, and have a thick GaN cap layer above thechannel layer that acts as a highly effective surface passivation layerto limit DC-to-RF dispersion and allows high output power, while a gaterecess allows vertical scaling for high-frequency operation. These highfrequency N-polar AlxGa1-xN/GaN HEMTs also have a secondary, thin AlGaNetch stop layer above the channel layer and under the thick GaN cap. Thethin etch stop is used to form the gate foot of these HEMTs, byaccurately terminating a deep dry etch of the gate recess or trench inthe capping material.

However, several disadvantages to incorporating this secondary AlGaNlayer include: the formation of a secondary parasitic channel at the topsecondary AlGaN layer/GaN cap layer interface in the access regions(between gate and source and between gate and drain); increased oxygenincorporation, alloy scattering and additional growth interruptsinherent to an additional Al-containing layer in the device structure;and channel charge depletion due to increased band bending at thesecondary AlGaN layer. Moreover, the selectivity between the etchmaterial and etch stop is not sufficiently high in etching systems,which prevents this process from being adopted in manufacturing. Thus,the thin AlGaN etch stop layer limits the performance of the knownN-Polar HEMTs and is not an effective etch stop for practical use.

SUMMARY

Embodiments of the present disclosure comprise improved high-frequencyand power performance high-scaled millimeter wave (mmW) N-polarAl_(x)Ga_(1-x)N/GaN HEMTs, as well as methods for fabricating same. SuchHEMTs can be integrated in MMIC technology. Embodiments of the presentdisclosure avoid the problems of the above-described HEMTs by altogetherremoving the thin etch stop layer from the layer structure in the accessregions of the HEMT, and instead complete the device with an additiveregrowth to insulate the channel from surface effects while maintaininga high aspect ratio. In addition to suppressing the detrimental effectsof the etch stop layer under the access regions, secondary benefits ofembodiments of this presentation include the elimination of etch damageunder the gate foot and provide a manufacturable method of achieving thedesired structure.

Embodiments of this presentation comprise, as illustrated for example inFIGS. 2, 3, 4, 5, 7, 10, 11, 14, 15, 18, 19, a HEMT (for example 30; 50;30′; 50′; 80; 85; 90; 96; 115; 120) comprising a channel layer (forexample 32; 118) of a first III-Nitride semiconductor material, grown ona N-polar surface (for example 33) of a back barrier layer (for example34) of a second III-Nitride semiconductor material; the secondIII-Nitride semiconductor material having a larger band gap than thefirst III-Nitride semiconductor material, such that a positively chargedpolarization interface and two-dimensional electron gas (for example 35)is obtained in the channel layer (for example 32; 118); a passivation,capping layer (for example 36; 36′, 36″), of said first III-Nitridesemiconductor material, formed on top of and in contact with a firstportion (for example 38) of a N-polar surface (for example 40) of saidchannel layer (for example 32; 118); a gate trench (for example 42)traversing the passivation, capping layer (for example 36), and endingat said N-polar surface (for example 40) of said channel layer (forexample 32; 118); and a gate conductor (for example 44) filling saidgate trench (for example 42).

According to embodiments of this presentation, as illustrated forexample in FIGS. 3, 5, 11, 15, 19 the HEMT (for example 50; 50′; 85; 96;120) comprises a thin layer (for example 52) of a third III-Nitridesemiconductor material in said gate trench (for example 42) between saidgate conductor (for example 44) and said N-polar surface (for example40) of said channel layer (for example 32, 118).

According to embodiments of this presentation, as illustrated forexample in FIGS. 2, 3, 4, 5, 7, 10, 11, 14, 15, 18, 19, saidpassivation, capping layer (for example 36; 36′, 36″), is a layer grownon said first portion (for example 38) of said N-polar surface (forexample 40) of said channel layer (for example 32; 118).

According to embodiments of this presentation, as illustrated forexample in FIGS. 2, 3, 4, 5, 7, 10, 11, 14, 15, 18, 19 said firstIII-Nitride semiconductor material is GaN and said second III-Nitridesemiconductor material is AlGaN.

According to embodiments of this presentation, as illustrated forexample in FIGS. 3, 5, 11, 15, 19 said third III-Nitride semiconductormaterial is one of AlN, InAlN, AlGaN and InAlGaN.

According to embodiments of this presentation, as illustrated forexample in FIGS. 2, 3, 4, 5, 7, 10, 11, 18, 19, the HEMT (for example30; 50; 30′; 50′; 80; 85; 115; 120) comprises a source contact layer(for example 45) and a drain contact layer (for example 46) of a fourthIII-Nitride semiconductor, formed on a second portion (for example 47)of said N-polar surface (for example 40) of said channel layer (forexample 32; 118) on opposite sides of said gate trench (for example 42).

According to embodiments of this presentation, as illustrated forexample in FIGS. 10, 11, in the HEMT (for example 80; 85) the channellayer (for example 32) has a first doping level and the source (forexample 45) and drain (for example 46) contact layers have a seconddoping level larger than the first doping level, wherein: a sourceaccess region of said passivation, capping layer (for example 36′),arranged between the source contact layer (for example 45) and the gatetrench (for example 42), has a third doping level whose magnitude isbetween those of the first and second doping levels; and a drain accessregion of said passivation, capping layer (for example 36″), arrangedbetween the drain contact layer (for example 46) and the gate trench(for example 42), has the first doping level.

According to embodiments of this presentation, as illustrated forexample in FIGS. 2, 3, 4, 5, 7, 10, 11, 18, 19, in the HEMT (for example30; 50; 30′; 50′; 80; 85; 115; 120) said source contact layer (forexample 45) and said drain contact layer (for example 46) are layersgrown on said second portion of said N-polar surface (for example 40) ofsaid channel layer (for example 32; 118).

According to embodiments of this presentation, as illustrated forexample in FIGS. 2, 3, 4, 5, 7, 10, 11, 18, 19, the HEMT (for example30; 50; 30′; 50′; 80; 85; 115; 120) comprises a source conductor (forexample 48) and a drain conductor (for example 49) in contact withrespectively said source contact layer (for example 45) and said draincontact layer (for example 46).

According to embodiments of this presentation, as illustrated forexample in FIGS. 2, 3, 4, 5, 7, 10, 11, 18, 19, in the HEMT (for example30; 50; 30′; 50′; 80; 85; 115; 120), said fourth III-Nitridesemiconductor material is n+ doped GaN or n+ doped InGaN.

According to embodiments of this presentation, as illustrated forexample in FIGS. 14; 15, the HEMT (for example 90; 96) comprises asource contact layer (for example 45) of a fourth III-Nitridesemiconductor, formed on a second portion of said N-polar surface (forexample 40) of said channel layer (for example 32) on a first side ofsaid gate trench (for example 42); and a drain contact layer (forexample 46′, 46″) of said fourth III-Nitride semiconductor, formed on aportion (for example 92; 98) of a top surface of said passivation,capping layer (for example 36), on a second side of said gate trench(for example 42) opposite said first side of said gate trench.

According to embodiments of this presentation, as illustrated forexample in FIGS. 14, 15, in the HEMT (for example 90; 96), said channellayer (for example 32) has a first doping level and said source (forexample 45) and drain (for example 46′; 46″) contact layers have asecond doping level larger than the first doping level, wherein: asource access region of said passivation, capping layer (for example36), arranged between the source contact layer (for example 45) and thegate trench (for example 42), has a third doping level comprised betweenthe first and second doping levels (i.e. a third doping level whosemagnitude is between those of the first and second doping levels); and adrain access region of said passivation, capping layer (for example 36),arranged between under the drain contact layer and the gate trench, hasthe first doping level.

According to embodiments of this presentation, as illustrated forexample in FIGS. 14, 15, in the HEMT (for example 90; 96), said sourcecontact layer (for example 45) and said drain contact layer (for example46′; 46″) are layers grown respectively on said second portion of saidN-polar surface (for example 40) of said channel layer (for example 32)and on said portion (for example 92, 98) of a top surface of saidcapping layer.

According to embodiments of this presentation, as illustrated forexample in FIGS. 14, 15, the HEMT (for example 90; 96) comprises asource conductor (for example 48) and a drain conductor (for example 49)in contact with respectively said source contact layer (for example 45)and said drain contact layer (for example 46′; 46″).

According to embodiments of this presentation, as illustrated forexample in FIGS. 14, 15, in the HEMT (for example 90; 96), said fourthIII-Nitride semiconductor material is n+ doped GaN or n+ doped InGaN.

According to embodiments of this presentation, as illustrated forexample in FIGS. 4; 5; 7, in the HEMT (for example 30′; 50′), a gateinsulator layer (for example 60) lines the side and bottom of said gateconductor (for example 44) in said gate trench (for example 42).

Other embodiments of this presentation relate to the following concepts:

Concept 1. A method of manufacturing a HEMT, the method comprising:

-   -   (as for example illustrated in FIGS. 8A, 20A), forming a channel        layer (for example 32; 118) of a first III-Nitride semiconductor        material on a N-polar surface of a back barrier layer (for        example 34) of a second III-Nitride semiconductor material, said        back barrier layer having been formed on a top surface of a        first epitaxial structure (for example 54, 56, 58);    -   (as for example illustrated in FIGS. 8B, 20B), forming a source        contact layer (for example 45) and a drain contact layer (for        example 46) of a third III-Nitride semiconductor on a first        portion (for example 47) of a N-polar surface (for example 40)        of the channel layer (for example 32), by:    -   forming on said N-polar surface (for example 40) of the channel        layer a contacts mask (for example 70) exposing said first        portion (for example 47) of said N-polar surface (for example        40) of the channel layer, but masking a second portion (for        example) 38 of said N-polar surface (for example 40) of the        channel layer;    -   (as for example illustrated in FIGS. 8C, 20C), growing said        source contact layer (for example 45) and said drain contact        layer (for example 46) on said first portion (for example 47) of        said N-polar surface (for example) 40 of the channel layer; and    -   removing said contacts mask (for example 70), thus exposing said        second portion (for example 38) of said N-polar surface (for        example 40) of the channel layer;    -   (as for example illustrated in FIG. 8D, 20D) forming a capping        layer mask (for example 72) on top of at least a portion of said        source contact layer (for example 45) and said drain contact        layer (for example 46) and on top of a gate region (for example        74) of said N-polar surface (for example) 40 of the channel        layer, located within said second portion (for example 38) of        said N-polar surface (for example) 40 of the channel layer, thus        exposing a part of said second portion (for example 38) of said        N-polar surface (for example) 40 of the channel layer;    -   (as for example illustrated in FIG. 8E, 20E), growing a capping        layer (for example 36) of said first III-Nitride semiconductor        material on top of and in contact with the exposed part of the        second portion (for example 38) of said N-polar surface (for        example) 40 of the channel layer, said capping layer (for        example 36) contacting at least side edges of said source        contact layer (for example 45) and said drain contact layer (for        example 46); and removing said capping layer mask (for example        72), thus forming a gate trench (for example 42) that traverses        said capping layer (for example 36) and ends at said N-polar        surface (for example 40) of the channel layer;    -   (as for example illustrated in FIG. 8F, 20F), filling said gate        trench (for example 42) with a gate conductor (for example 44);        and    -   forming a source conductor (for example 48) and a drain        conductor (for example 49) respectively on top of said source        contact layer (for example 45) and said drain contact layer (for        example 46).

Concept 2. The method of Concept 1, wherein said first epitaxialstructure (54, 56, 58) comprises a buffer layer (for example 58) formedon top of a nucleation layer (for example 56) formed on top of asubstrate (for example 54).

Concept 3. The method of Concept 1, wherein (as illustrated for examplein FIG. 8D; 20D) said capping layer mask (for example 72) is arranged toexpose a portion of said source contact layer (for example 45) and aportion of said drain contact layer (for example 46) neighboring saidexposed part of said second portion (for example 38) of said N-polarsurface (for example) 40 of the channel layer, whereby (as illustratedfor example in FIG. 8E) said capping layer (for example 36) contactssaid portion of said source contact layer (for example 45) and saidportion of said drain contact layer (for example 46).

Concept 4. The method of Concept 1, wherein (as illustrated for examplein FIG. 8F; 20F) said filling said gate trench (for example 42) with agate conductor (for example 44) is done after forming a gate dielectric(for example 60) on the bottom and edges of the gate trench (for example42).

Concept 5. The method of Concept 1, wherein (as illustrated for examplein FIG. 20A) said channel layer is a graded channel layer (for example118). In particular, the graded channel layer is a compositionallygraded channel layer whose composition (e.g., Al mole fraction in AlGaN)varies along its thickness/height.

Concept 6. The method of Concept 1, wherein said first III-Nitridesemiconductor material is GaN, said second III-Nitride semiconductormaterial is AlGaN, and said third III-Nitride semiconductor material isn+ doped GaN or n+ doped InGaN.

Concept 7. A method of manufacturing a HEMT, the method comprising:

-   -   (as for example illustrated in FIGS. 12A, 13A), forming a        channel layer (for example 32) of a first III-Nitride        semiconductor material on a N-polar surface of a back barrier        layer (for example 34) of a second III-Nitride semiconductor        material, said back barrier layer having been formed on a top        surface of a first epitaxial structure (for example 54, 56, 58);    -   (as for example illustrated in FIGS. 12B, 13D), forming a source        contact layer (for example 45) and a drain contact layer (for        example 46) of a third III-Nitride semiconductor on a first        portion (for example 47) of a N-polar surface (for example 40)        of the channel layer (for example 32), by:    -   forming on said N-polar surface (for example 40) of the channel        layer a contacts mask (for example 70) exposing said first        portion (for example 47) of said N-polar surface (for example        40) of the channel layer, but masking a second portion (for        example) 38 of said N-polar surface (for example 40) of the        channel layer;    -   (as for example illustrated in FIGS. 12C, 13E), growing said        source contact layer (for example 45) and said drain contact        layer (for example 46) on said first portion (for example 47) of        said N-polar surface (for example) 40 of the channel layer; and    -   removing said contacts mask (for example 70), thus exposing said        second portion (for example 38) of said N-polar surface (for        example 40) of the channel layer;    -   (as for example illustrated in FIG. 12D, 13F) forming a first        capping layer mask (for example 72′) on top of at least a        portion of said source contact layer (for example 45) and        covering completely said drain contact layer (for example 46)        and a gate region of said N-polar surface (for example) 40 of        the channel layer, located within said second portion (for        example 38) of said N-polar surface (for example) 40 of the        channel layer, thus exposing a first part of said second portion        (for example 38′) of said N-polar surface (for example) 40 of        the channel layer, between said gate region and said source        contact layer (for example 45);    -   (as for example illustrated in FIG. 12E, 13G), growing a first        portion of capping layer (for example 36′) of said first        III-Nitride semiconductor material on top of and in contact with        the exposed first part of the second portion (for example 38′)        of said N-polar surface (for example 40) of the channel layer,        said first portion of capping layer (for example 36′) contacting        at least side edges of said source contact layer (for example        45); and removing said first capping layer mask (for example        72′);    -   (as for example illustrated in FIG. 12F, 13H) forming a second        capping layer mask (for example 72″) on top of at least a        portion of said drain contact layer (for example 46) and        covering completely said source contact layer (for example 45)        and said gate region of said N-polar surface (for example) 40 of        the channel layer, thus exposing a second part of said second        portion (for example 38″) of said N-polar surface (for example)        40 of the channel layer, between said gate region and said drain        contact layer (for example 46);    -   (as for example illustrated in FIG. 12G, 13I), growing a second        portion of capping layer (for example 36″) of said first        III-Nitride semiconductor material on top of and in contact with        the exposed second part of the second portion (for example 38″)        of said N-polar surface (for example 40) of the channel layer,        said second portion of capping layer (for example 36″)        contacting at least side edges of said drain contact layer (for        example 46); and removing said second capping layer mask (for        example 72″), thus forming a gate trench (for example 42) that        traverses said capping layer (for example 36′, 36″) and ends at        said N-polar surface (for example 40) of the channel layer;    -   (as for example illustrated in FIG. 12H, 13J), filling said gate        trench (for example 42) with a gate conductor (for example 44);        and    -   forming a source conductor (for example 48) and a drain        conductor (for example 49) respectively on top of said source        contact layer (for example 45) and said drain contact layer (for        example 46).

Concept 8. The method of Concept 7, wherein said first epitaxialstructure (54, 56, 58) comprises a buffer layer (for example 58) formedon top of a nucleation layer (for example 56) formed on top of asubstrate (for example 54).

Concept 9. The method of Concept 7, wherein (as illustrated for examplein FIGS. 12D and 12F) said first and second capping layer masks (forexample 72′, 72″) are arranged to expose a portion of said sourcecontact layer (for example 45) and a portion of said drain contact layer(for example 46) neighboring said exposed parts of said second portion(for example 38′, 38″) of said N-polar surface (for example) 40 of thechannel layer, whereby (as illustrated for example in FIG. 12G) saidcapping layer (for example 36′, 36″) contacts said portion of saidsource contact layer (for example 45) and said portion of said draincontact layer (for example 46).

Concept 10. The method of Concept 7, wherein (as illustrated for examplein FIG. 12H) said filling said gate trench (for example 42) with a gateconductor (for example 44) is done after forming a gate dielectric (forexample 60) on the bottom and edges of the gate trench (for example 42).

Concept 11. The method of Concept 7, further comprising (as illustratedfor example in FIGS. 13A, 13B, 13C) growing a gate barrier layer (forexample 76) of a fourth III-Nitride semiconductor on top of said N-polarsurface (for example 40) of the channel layer (for example 32) afterforming said channel layer; and, with a gate mask (for example 72),removing said gate barrier layer (for example 76) from said N-polarsurface (for example) 40 of the channel layer except above said gateregion, whereby said gate barrier layer covers the bottom of said gatetrench (for example 42).

Concept 12. The method of Concept 7, wherein said first III-Nitridesemiconductor material is GaN, said second III-Nitride semiconductormaterial is AlGaN, and said third III-Nitride semiconductor material isn+ doped GaN or n+ doped InGaN.

Concept 13. The method of claim Concept 11, wherein said firstIII-Nitride semiconductor material is GaN, said second III-Nitridesemiconductor material is AlGaN, said third III-Nitride semiconductormaterial is n+ doped GaN or n+ doped InGaN, and said fourth III-Nitridesemiconductor is AlGaN.

Concept 14. The method of claim 7, wherein the channel layer (forexample 32) has a first doping level and the source (for example 45) anddrain (for example 46) contact layers have a second doping level largerthan the first doping level, wherein: a source access region of saidpassivation, capping layer (for example 36′), arranged between thesource contact layer (for example 45) and the gate trench (for example42), has a third doping level whose magnitude is between those of thefirst and second doping levels; and a drain access region of saidpassivation, capping layer (for example 36″), arranged between the draincontact layer (for example 46) and the gate trench (for example 42), hasthe first doping level.

Concept 15. A method of manufacturing a HEMT, the method comprising:

-   -   (as for example illustrated in FIG. 16A), forming a channel        layer (for example 32) of a first III-Nitride semiconductor        material on a N-polar surface of a back barrier layer (for        example 34) of a second III-Nitride semiconductor material, said        back barrier layer having been formed on a top surface of a        first epitaxial structure (for example 54, 56, 58);    -   (as for example illustrated in FIG. 16B), forming a capping        layer mask (for example 102) masking a gate region (for example        104) and a source contact region (for example 103) of a N-polar        surface (for example 40) of the channel layer (for example 32),        thus leaving exposed a first portion (for example 105) of said        N-polar surface (for example 40) of the channel layer, between        said gate region and said source contact region, and a second        portion (for example 106) of said N-polar surface (for example        40) of the channel layer, on a side of said gate region opposite        said source contact region;    -   (as for example illustrated in FIG. 16B), growing a capping        layer (for example 36) of said first III-Nitride semiconductor        material on top of and in contact with the exposed portions (for        example 105, 106) of said N-polar surface (for example) 40 of        the channel layer, and removing said capping layer mask (for        example 72), thus forming a gate trench (for example 42) that        traverses said capping layer (for example 36) and ends at said        N-polar surface (for example 40) of the channel layer;    -   (as for example illustrated in FIG. 16D), forming a contacts        mask (for example 70) above the gate trench and most of the        capping layer (for example 36) such as to expose said source        contact region (for example 103) as well as a portion of the        capping layer (for example 92) distal from said gate recess;    -   (as for example illustrated in FIG. 16E), forming a source        contact layer (for example 45) on said source contact region        (for example 103) and forming a drain contact layer (for example        46′) on top of the exposed portion of the capping layer (for        example 92), and removing the contacts mask, thus exposing the        gate trench (for example 42); and    -   (as for example illustrated in FIG. 16F) forming a source        conductor (for example 48) and a drain conductor (for example        49) respectively on top of said source contact layer (for        example 45) and said drain contact layer (for example 46′), and        filling the gate trench (for example 42) with a conductor (for        example 44).

Concept 16. The method of Concept 15, wherein said first epitaxialstructure (54, 56, 58) comprises a buffer layer (for example 58) formedon top of a nucleation layer (for example 56) formed on top of asubstrate (for example 54).

Concept 17. The method of Concept 15, wherein (as illustrated forexample in FIG. 16F) said filling said gate trench (for example 42) witha gate conductor (for example 44) is done after forming a gatedielectric (for example 60) on the bottom and edges of the gate trench(for example 42).

Concept 18. The method of Concept 15, wherein said first III-Nitridesemiconductor material is GaN, said second III-Nitride semiconductormaterial is AlGaN, and said third III-Nitride semiconductor material isn+ doped GaN or n+ doped InGaN.

Concept 19. A method of manufacturing a HEMT, the method comprising:

-   -   (as for example illustrated in FIG. 17A), forming a channel        layer (for example 32) of a first III-Nitride semiconductor        material on a N-polar surface of a back barrier layer (for        example 34) of a second III-Nitride semiconductor material, said        back barrier layer having been formed on a top surface of a        first epitaxial structure (for example 54, 56, 58), and forming        a gate barrier layer (for example 76) of a third III-Nitride        semiconductor on top of said N-polar surface (for example 40) of        the channel layer (for example 32)    -   (as for example illustrated in FIG. 17B), forming a gate mask        (for example 72) exposing said gate barrier layer (for example        76) except above a gate region of said N-polar surface (for        example 40) of the channel layer;    -   (as for example illustrated in FIG. 17C), removing said gate        barrier layer (for example 76) from said N-polar surface (for        example) 40 of the channel layer except above said gate region;    -   (as for example illustrated in FIG. 17D), forming a capping        layer mask (for example 110) masking a source contact region        (for example 103) of said N-polar surface (for example 40) of        the channel layer, thus leaving exposed a first portion (for        example 105) of said N-polar surface (for example 40) of the        channel layer, between said gate region and said source contact        region, and a second portion (for example 106) of said N-polar        surface (for example 40) of the channel layer, on a side of said        gate region opposite said source contact region;    -   (as for example illustrated in FIG. 17E), growing a capping        layer (for example 36) of said first III-Nitride semiconductor        material on top of and in contact with the exposed portions (for        example 105, 106) of said N-polar surface (for example) 40 of        the channel layer, and removing said gate mask (for example 72)        and said capping layer mask (for example 110), thus forming a        gate trench (for example 42) that traverses said capping layer        (for example 36) and ends at said N-polar surface (for example        40) of the channel layer, wherein a portion (for example 52) of        said gate barrier layer lies at the bottom of said gate trench        (for example 42);    -   (as for example illustrated in FIG. 17F), forming a contacts        mask (for example 70) above the gate trench and most of the        capping layer (for example 36) such as to expose said source        contact region (for example 103) as well as a portion of the        capping layer (for example 92) distal from said gate recess;    -   (as for example illustrated in FIG. 17G), forming a source        contact layer (for example 45) on said source contact region        (for example 103) and forming a drain contact layer (for example        46′) on top of the exposed portion of the capping layer (for        example 92), and removing the contacts mask, thus exposing the        gate trench (for example 42); and    -   (as for example illustrated in FIG. 17H) forming a source        conductor (for example 48) and a drain conductor (for example        49) respectively on top of said source contact layer (for        example 45) and said drain contact layer (for example 46′), and        filling the gate trench (for example 42) with a conductor (for        example 44).

Concept 20. The method of Concept 19, wherein said first epitaxialstructure (54, 56, 58) comprises a buffer layer (for example 58) formedon top of a nucleation layer (for example 56) formed on top of asubstrate (for example 54).

Concept 21. The method of Concept 19, wherein (as illustrated forexample in FIG. 16F) said filling said gate trench (for example 42) witha gate conductor (for example 44) is done after forming a gatedielectric (for example 60) on the bottom and edges of the gate trench(for example 42).

Concept 22. The method of Concept 19, wherein said first III-Nitridesemiconductor material is GaN, said second III-Nitride semiconductormaterial is AlGaN, and said third III-Nitride semiconductor material isn+ doped GaN or n+ doped InGaN.

Concept 23. A method of manufacturing a HEMT, the method comprising:

-   -   (as for example illustrated in FIG. 9A; 21A), forming a channel        layer (for example 32; 118) of a first III-Nitride semiconductor        material on a N-polar surface of a back barrier layer (for        example 34) of a second III-Nitride semiconductor material, said        back barrier layer having been formed on a top surface of a        first epitaxial structure (for example 54, 56, 58);    -   (as for example illustrated in FIG. 9B; 21B) forming a capping        layer mask (for example 72) on top of a gate region (for example        74) of said N-polar surface (for example) 40 of the channel        layer, thus exposing a first portion of said N-polar surface        (for example) 40 of the channel layer;    -   (as for example illustrated in FIG. 9D; 21D), growing a capping        layer (for example 36) of said first III-Nitride semiconductor        material on top of and in contact with the exposed first portion        of said N-polar surface (for example) 40 of the channel layer;        and removing said capping layer mask (for example 72), thus        forming a gate trench (for example 42) that traverses said        capping layer (for example 36) and ends at said N-polar surface        (for example 40) of the channel layer;    -   (as for example illustrated in FIG. 9E; 21E), forming a source        contact layer (for example 45) and a drain contact layer (for        example 46) of a third III-Nitride semiconductor on distal parts        of said first portion of said N-polar surface (for example 40)        of the channel layer, by:    -   forming on said gate trench (for example 42) and on proximal        parts of said capping layer (for example 36) a contacts mask        (for example 70) exposing distal parts of said capping layer        (for example 36);    -   (as for example illustrated in FIG. 9F; 21F), etching away said        distal parts of said capping layer (for example 36), thus        exposing said distal parts of said first portion of said N-polar        surface (for example 40) of the channel layer;    -   (as for example illustrated in FIG. 9G; 21G), growing said        source contact layer (for example 45) and said drain contact        layer (for example 46) on said distal parts of said first        portion of said N-polar surface (for example 40) of the channel        layer; and    -   removing said contacts mask (for example 70), thus exposing        again said gate trench (for example 42);    -   (as for example illustrated in FIG. 9H; 21H), filling said gate        trench (for example 42) with a gate conductor (for example 44);        and    -   forming a source conductor (for example 48) and a drain        conductor (for example 49) respectively on top of said source        contact layer (for example 45) and said drain contact layer (for        example 46).

Concept 24. The method of Concept 23, further comprising growing a gatebarrier layer (for example 76) of a fourth III-Nitride semiconductor ontop of said channel layer (for example 32) before said forming a cappinglayer mask (for example 72), whereby said gate barrier layer covers thebottom of said gate trench (for example 42).

Concept 25. The method of Concept 23, wherein said first epitaxialstructure (54, 56, 58) comprises a buffer layer (for example 58) formedon top of a nucleation layer (for example 56) formed on top of asubstrate (for example 54).

Concept 26. The method of Concept 23, wherein (as illustrated forexample in FIG. 9H; 21H) said filling said gate trench (for example 42)with a gate conductor (for example 44) is done after forming a gatedielectric (for example 60) on the bottom and edges of the gate trench(for example 42).

Concept 27. The method of Concept 23, further comprising (as illustratedfor example in FIGS. 21A, 21B, 21C) growing a gate barrier layer (forexample 76) of a fourth III-Nitride semiconductor on top of said N-polarsurface (for example 40) of the channel layer (for example 118) afterforming said channel layer; and, with a gate mask (for example 72),removing said gate barrier layer (for example 76) from said N-polarsurface (for example) 40 of the channel layer except above said gateregion, whereby said gate barrier layer covers the bottom of said gatetrench (for example 42).

Concept 28. The method of Concept 23, wherein (as illustrated forexample in FIG. 21A) said channel layer is a graded channel layer (forexample 118). In particular, the graded channel layer is acompositionally graded channel layer whose composition (e.g., Al molefraction in AlGaN) varies along its thickness/height.

Concept 29. The method of Concept 23, wherein said first III-Nitridesemiconductor material is GaN, said second III-Nitride semiconductormaterial is AlGaN, and said third III-Nitride semiconductor material isn+ doped GaN or n+ doped InGaN, and said fourth III-Nitridesemiconductor is AlGaN.

Concept 30. The method of Concept 27, wherein said first III-Nitridesemiconductor material is GaN, said second III-Nitride semiconductormaterial is AlGaN, said third III-Nitride semiconductor material is n+doped GaN or n+ doped InGaN, and said fourth III-Nitride semiconductoris AlGaN.

This Summary is provided to introduce a selection of concepts in asimplified form that are further described below in the DetailedDescription.

BRIEF DESCRIPTION OF THE DRAWINGS

Various embodiments in accordance with the present disclosure will bedescribed with reference to the drawings, in which:

FIG. 1A illustrates a known N-polar HEMT.

FIGS. 1B to 1D illustrate a known N-polar HEMT and some of its energybands.

FIG. 2 illustrates an embodiment of a HEMT according to thispresentation.

FIG. 3 illustrates an embodiment of a HEMT according to thispresentation.

FIG. 4 illustrates an embodiment of the HEMT of FIG. 2.

FIG. 5 illustrates an embodiment of the HEMT of FIG. 3.

FIGS. 6A and 6B show band diagram simulations through an access regionof a HEMT according to embodiments of this presentation.

FIG. 7 shows the location of the access region used for generating FIG.6.

FIGS. 8A to 8F illustrate fabrication steps of the HEMT of FIG. 4.

FIGS. 9A to 9H illustrate fabrication steps of the HEMT of FIG. 5.

FIG. 10 illustrates an embodiment of a HEMT according to thispresentation.

FIG. 11 illustrates an embodiment of a HEMT according to thispresentation.

FIGS. 12A to 12H illustrate fabrication steps of the HEMT of FIG. 10.

FIGS. 13A to 13J illustrate fabrication steps of the HEMT of FIG. 11.

FIG. 14 illustrates an embodiment of a HEMT according to thispresentation.

FIG. 15 illustrates an embodiment of a HEMT according to thispresentation.

FIGS. 16A to 16F illustrate fabrication steps of the HEMT of FIG. 14.

FIGS. 17A to 17H illustrate fabrication steps of the HEMT of FIG. 15.

FIG. 18 illustrates an embodiment of a HEMT according to thispresentation.

FIG. 19 illustrates an embodiment of a HEMT according to thispresentation.

FIGS. 20A to 20F illustrate fabrication steps of the HEMT of FIG. 18.

FIGS. 21A to 21H illustrate fabrication steps of the HEMT of FIG. 19.

FIG. 22 illustrates the HEMT of FIG. 14 and shows locations of interestused in FIG. 23.

FIGS. 23A to 23C illustrate energy band diagrams at the locations ofinterest shown in FIG. 22.

The figures are drawn to clearly illustrate the relevant aspects of theembodiments and are not necessarily drawn to scale.

DETAILED DESCRIPTION OF EMBODIMENTS

In the following detailed description, reference is made to theaccompanying drawings which form a part hereof, and in which are shownby way of illustration specific embodiments in which the invention maybe practiced. These embodiments are described in sufficient detail toenable those skilled in the art to practice the invention, and it is tobe understood that other embodiments may be utilized and thatstructural, logical and electrical changes may be made without departingfrom the spirit and scope of the invention. The following detaileddescription is therefore not to be taken in a limiting sense, and thescope of the invention is defined only by the appended claims andequivalents thereof. Like numbers in the figures refer to likecomponents, which should be apparent from the context of use.

FIG. 1A illustrates a known N-polar HEMT 10 using a dielectricpassivation capping layer 11 (SiN illustrated). While speciallydeveloped dielectric passivation somewhat improves the performance ofGaN HEMTs, it does not eliminate dc-RF dispersion (also known as currentcollapse) and results in reduced HEMT output power at any operatingfrequency. Moreover, dielectric passivation and field plates—which areused to reduce dc-RF dispersion in low-frequency GaN HEMTs—aredetrimental to the performance of high-frequency GaN HEMTs. The highlyscaled GaN HEMTs used in high-frequency applications are particularlysensitive to surface conditions. Dielectric passivation in GaN HEMTsonly mitigates—but does not eliminate—the detrimental dc-RF dispersionin the performance of the HEMT at any frequency. An effective method ofeliminating dc-RF dispersion is replacing a dielectric passivationcapping layer with semiconductor passivation capping layer.

FIG. 1B illustrates a known N-polar HEMT 12 using a semiconductorpassivation 13 (GaN illustrated) to address the shortcomings of the HEMT10 illustrated in FIG. 1A. In order to stop the gate trench etching frometching the channel layer 14 (GaN illustrated), an etch stop layer (I)made out of another semiconductor (AlGaN illustrated) is formed on topof the channel 14. FIG. 1C illustrates the energy band diagrams atequilibrium in the gate recessed region and FIG. 1D illustrates theenergy band diagrams in the drain access region. i.e. between the gateand drain. As illustrated in FIGS. 1B and 1D, the (AlGaN) etch stoplayer (reference I, FIG. 1B) pulls up (reference II, FIG. 1D) theconduction band, thus depleting the 2DEG/channel of the HEMT. Further,the (AlGaN) etch stop layer (reference I, FIG. 1B) creates a parasiticelectron channel (reference III, FIG. 1D) that can detrimentally affectthe performance of the HEMT.

FIG. 2 illustrates an embodiment of a HEMT 30 according to thispresentation, comprising a channel layer 32 of a first III-Nitridesemiconductor material (e.g. GaN), grown on a N-polar surface 33 of aback barrier layer 34 of a second III-Nitride semiconductor material(e.g. AlGaN). According to an embodiment of this presentation, thesecond III-Nitride semiconductor material (e.g. AlGaN) has a larger bandgap than the first III-Nitride semiconductor material (e.g. GaN), suchthat a positively charged polarization interface and two-dimensionalelectron gas 35 is obtained in the channel layer 32. According toembodiments of this presentation, the back barrier 34 can be anycoherently strained layer (i.e. a layer so thin that lattice constantmismatches do not result in lattice mismatch crystal defects but arecontained by lattice stretching.), or combination of coherently strainedlayers. According to embodiments of this presentation, in case the firstIII-Nitride semiconductor material comprises GaN, the back barrier 34can be composed of any Al containing III-nitride material and of largerband gap than GaN such that a positively charged polarization interfaceand two dimensional electron gas 35 is obtained in the channel 32 abovethe interface of the back barrier 34 with the GaN channel 32. Accordingto embodiments of this presentation, channel 32 can be formed atop theback barrier layer as a final layer of an initial epitaxial structuregrowth. According to embodiments of this presentation, as channel layer32 is grown on a N-polar surface 33 of back barrier layer 34, a topsurface 40 of channel layer 32 is also a N-polar surface.

According to an embodiment of this presentation, HEMT 30 furthercomprises a capping layer 36 (“regrowth A”) of said first III-Nitridesemiconductor material, formed on top of and in contact with a firstportion 38 of N-polar surface 40 of channel layer 32. According to anembodiment of this presentation, HEMT 30 further comprises: a gatetrench 42 traversing the capping layer 36 and ending at the N-polarsurface 40 of the channel layer 32; and a gate conductor 44 filling gatetrench 42. According to embodiments of this presentation, the materialdescribed as AlGaN is effectively an Al(x)Ga(1-x)N material. Accordingto embodiments of this presentation, the regrown capping layer 36functions to passivate surface traps, to prevent DC-to-RF dispersion, toincrease 2DEG density in underlying epitaxial layers, and to preventoxidation of underlying Al-containing layers.

According to embodiments of this presentation, an “N-polar” face orsurface of a III-nitride semiconductor layer is the Nitrogen-polar faceof the III-Nitride semiconductor layer. According to embodiments of thispresentation, HEMT 30 further comprises a source (ohmic) contact layer45 and a drain (ohmic) contact layer 46 of a further III-Nitridesemiconductor, formed on a second portion 47 of the N-polar surface 40of channel layer 32, beyond first portion 38, on opposite sides of gatetrench 42. According to embodiments of this presentation, HEMT 30further comprises a source conductor 48 and a drain conductor 49 incontact with respectively the source contact layer 45 and the draincontact layer 46. According to embodiments of this presentation, thefurther III-Nitride semiconductor material forming contact layers 45 and46 is n+ doped GaN or n+ doped InGaN. As detailed hereafter, accordingto embodiments of this disclosure, the n+ doping concentration of theohmic contact regions 45 and 46 can be comprised between 1×10{circumflexover ( )}19 and 9×10{circumflex over ( )}20 cm-3 (one times 10 to thepower 19 to 9 times 10 to the power 20 per cubic cm).

According to embodiments of this presentation, the gate conductor 44 ispart of a “T-shape” gate structure (or “T-gate”) as for exampleillustrated in FIG. 4 hereafter, where a top portion of the gatestructure (gate head) is broader than a middle portion of the gatestructure. Optionally, the gate structure may also consist of a “y-gate”(“y” shape) as for example illustrated in FIG. 3. According toembodiments of this presentation, the gate structure comprises a Pt/Auor a Ni/Au structure, or any other metallization layer used formanufacturing the HEMT. According to embodiments of this disclosure, theback barrier layer 34 of HEMT 30 can be formed on a N-polar surface 53of a substrate 54. Substrate 54 can be SiC or Si, sapphire, GaN, AlN,diamond.

FIG. 3 illustrates an embodiment of a HEMT 50 according to thispresentation, which is essentially identical to HEMT 30 of FIG. 2, butwhich additionally comprises a thin layer 52 (“gate barrier”) of a stillfurther III-Nitride semiconductor material (for example one of AlN,InAlN, AlGaN and InAlGaN) in the gate trench 42 between the gateconductor 44 and the N-polar surface 40 of the channel layer 32.According to embodiments of this presentation, gate barrier 52 is acoherently-strained epitaxial layer. According to embodiments of thispresentation, gate barrier 52 improves the channel mobility and theblocking of charge from the gate. According to embodiments of thisdisclosure, the back barrier layer 34 of HEMT 50 can be formed on aN-polar surface 53 of a substrate 54. Substrate 54 can be SiC or Si,sapphire, GaN, AlN, diamond. According to embodiments of thispresentation, a nucleation layer (not shown in FIG. 2 or 3) can beformed on top of and in contact with the N-polar surface 53 of thesubstrate 54, and a buffer layer (not shown in FIG. 2 or 3) can beformed on top of and in contact with the nucleation layer below thebarrier layer 34.

FIG. 4 illustrates an embodiment of a HEMT 30′ similar to HEMT 30 ofFIG. 2, additionally showing a nucleation layer 56 formed on top of andin contact with the N-polar surface 53 of the substrate 54, and a bufferlayer 58 formed on top of and in contact with the nucleation layer 56,before forming the barrier layer 34 on top of and in contact with thebuffer layer 58. HEMT 30′ can optionally comprise a gatedielectric/insulator layer 60 that lines at least the sides and bottomof the gate conductor 44 in the gate trench. Optionally, the insulatorlayer 60 can also cover the top surface of the cap layer 36. Accordingto embodiments of this presentation, gate dielectric 60 can comprise alayer of SiN or Al2O3, or of AlN, HfO2, SiO2, or some combinationthereof.

FIG. 5 illustrates a HEMT 50′ similar to the HEMT 50 of FIG. 3,additionally showing a nucleation layer 56 formed on top of and incontact with the N-polar surface 53 of the substrate 54, and a bufferlayer 58 formed on top of and in contact with the nucleation layer 56before forming the barrier layer 34 on top of and in contact with thebuffer layer 58. HEMT 50′ can optionally comprise a gatedielectric/insulator layer 60 as the one described in relation with FIG.4.

FIGS. 6A and 6B show band diagram simulations through an access region(region between gate and source, simulations made at the dashed linemark A-A′ illustrated in FIG. 7) of a HEMT 30′ according to embodimentsof this presentation. Band diagrams are shown for three different GaNcap thicknesses (10, 20, and 40 nm) and three different Si delta-dopinglevels (10¹⁹ cm-3, 5·10¹⁹ cm-3 and 10²⁰ cm-3). As illustrated in FIG.6A, both the Si delta doping and the thickness of the regrowth layer A(GaN cap) shape the electric field in the channel access region in amanner that for example increases charge during dc conditions. FIG. 6Billustrates the changes of the charge in a portion of the access region.The result of increased charge is a reduction in parasitic accessresistance and an increase in drain current. The increased charge fromelectric field shaping also screens the effect of the traps that causeundesirable current collapse during operation. The net result of thiselectric field shaping is higher device output power.

As illustrated in FIGS. 6A and 6B, and because there is no semiconductor(AlGaN) etch stop to pull up the conduction band, contrary to whathappened in the prior art HEMT of e.g. FIG. 1B, a HEMT according to thispresentation shows a higher 2DEG density in the access regions relativeto the prior art, which allows increasing the current and power in thedevice. As outlined above, Si delta doping may be used at thetermination of the GaN channel layer of the initial epitaxial structureor at the beginning of a regrowth step to intentionally shape theelectric fields near the channel and in the access regions near thegate. Delta-Doping is a technique, usually used in MOCVD growth, thatcan be used to get thin layers of high dopant concentration or, ifcombined with annealing, to get homogeneous doping with very high dopantconcentration. A delta-doping procedure can consist of multiple growthsteps, where the host material and dopant sources are openedintermittently. Process variants leave the host material source open allthe time and just open/close the dopant source. This process allowsobtaining relatively thick nominally undoped layers interrupted byrelatively thin layers with very high dopant concentration.

FIG. 7 shows with a dashed line A-A′ the location of the access regionof a HEMT 30′ according to this presentation, used for generating theband diagram simulations of FIGS. 6A and 6B.

FIGS. 8A to 8F illustrate steps of a method of fabrication of the HEMT30′ of FIG. 4, the method including: forming channel layer 32 (of thefirst III-Nitride semiconductor material) on the N-polar surface of backbarrier layer 34 (of the second III-Nitride semiconductor material),itself formed on the substrate 54 and eventually buffer layer 58 andnucleation layer 56. According to embodiments of this presentation,these first steps equate to forming a first epitaxial structure (FIG.8A).

According to embodiments of this presentation, the method furthercomprises forming source contact layer 45 and drain contact layer 46 (ofthe fourth III-V semiconductor) on a portion 47 of the N-polar surface40 of the channel layer 32, by forming on said N-polar surface 40 acontacts mask 70 exposing said portion 47 of N-polar surface 40, butmasking a portion 38 of N-polar surface 40 (FIG. 8B). Source contactlayer 45 and drain contact layer 46 are then regrown (grown epitaxially)on the exposed portion 47 of surface 40; then mask 70 is removed (FIG.8C).

According to embodiments of this presentation, the method furthercomprises forming a capping layer mask 72 exposing portion 38 of surface40, except a gate region 74 of surface 40, located within portion 38.According to embodiments of this presentation, mask 72 is also arrangedto expose small sections of source contact layer 45 and drain contactlayer 46 neighboring the portion 38 of surface 40 (FIG. 8D).

According to embodiments of this presentation, the method furthercomprises growing capping layer 36 on top of and in contact with portion38 of surface 40 (as well as on top of the sections of contact layer 45and drain contact layer 46 left exposed by mask 72; then and removingmask 72 (FIG. 8E). According to embodiments of this presentation, themethod removing of mask 72 notably forms the gate trench 42 thattraverses capping layer 36 and ends at surface 40.

The method can then comprise finalizing HEMT 30′, by filling gate trench42 with gate conductor 44, eventually after forming a gate dielectric 60on the bottom and edges of the gate trench (and eventually on top ofcapping layer 36, as illustrated); as well as by forming sourceconductor 48 and drain conductor 49 (FIG. 8F). As outlined above, gateconductor 44 can be part of a “T-shaped gate” as shown in FIG. 8.

It is to be noted that the forming of the source and drain contacts 45,46 can alternatively take place after the forming of the capping layer36. In such an embodiment, mask 72 only covers the gate region 74 andthe capping layer is also formed in areas where the source and draincontacts are to be formed. Mask 70 is then formed on top of the cappinglayer to etch the capping layer and free the areas where the source anddrain contacts 45, 46 are then formed. According to embodiments of thispresentation, etch of the capping layer can be performed using dryplasma etching. The masks are arranged such that no gap exists at theinterface between capping layer 36 and source contact layer 45 or at theinterface between capping layer 36 and drain contact layer 46.

According to embodiments of this presentation, channel layer 32 has afirst doping level, source and drain contact layers 45, 46 have a seconddoping level larger than the first doping level, and capping layer 36has the first doping level.

FIGS. 9A to 9H illustrate fabrication steps of the HEMT 50′ of FIG. 5,the method including, as in FIGS. 8A to 8F, forming a first epitaxialstructure comprising channel layer 32 on the N-polar surface of backbarrier layer 34, itself on the substrate 54 and eventually buffer layer58 and nucleation layer 56. Further, according to this embodiment, agate barrier layer 76 (e.g. AlGaN) is formed on top of channel layer 32(FIG. 9A).

According to embodiments of this presentation, the method furthercomprises forming a capping layer mask 72 above a gate region 74 ofsurface 40 of channel layer 32. (FIG. 9B). The method then comprisesetching away gate barrier layer 76 using mask 72, thus forming gatebarrier 52 above gate region 74. (FIG. 9C).

According to embodiments of this presentation, the method furthercomprises growing capping layer 36 everywhere on top surface 40 (excepton the portion covered by mask 72); then removing mask 72 (FIG. 9D).According to embodiments of this presentation, the method of removingmask 72 notably forms the gate trench 42 that traverses capping layer 36and ends at surface 40, with gate barrier 52 arranged at the bottom oftrench 42 on surface 40.

According to embodiments of this presentation, the method furthercomprises forming source contact layer 45 and drain contact layer 46 byforming a contacts mask 70 on the capping layer 36 and the gate trench42, exposing only portions 47 of the capping layer 36 above areas ofsurface 40 where the source and drain contacts are to be formed (FIG.9E). The capping layer 36 is then etched using mask 70, thus exposingthe areas of surface 40 where the source and drain contacts are to beformed (FIG. 9F). Source contact layer 45 and drain contact layer 46 arethen regrown (grown epitaxially) on the exposed portion 47 of surface40; before mask 70 is removed (FIG. 9G).

The method can then comprise finalizing HEMT 50′, by filling gate trench42 with gate conductor 44, eventually after forming a gate dielectric 60on the bottom and edges of the gate trench (and eventually on top ofcapping layer 36, as illustrated); as well as by forming sourceconductor 48 and drain conductor 49 (FIG. 9H). As outlined above, gateconductor 44 can be part of a “T-shaped gate” as illustrated in FIG. 9.

It is to be noted that the forming of the source and drain contacts 45,46 can alternatively take place before the forming of the capping layer46, similarly to what is disclosed in relation with FIG. 8.

FIG. 10 illustrates an embodiment of a HEMT 80 according to thispresentation, which is essentially identical to the HEMT 30 describedabove, except that the capping layer 36 between the gate 44 and thesource contact layer 45 forms a source access region 36′ having a givendoping and the capping layer 36 between the gate 44 and the draincontact layer 46 forms a drain access region 36″ having a differentdoping. According to this embodiment, channel layer 32 has a firstdoping level and source and drain contact layers 45, 46 have a seconddoping level larger than the first doping level, the source accessregion 36′ has a third doping level comprised between the first andsecond doping levels; (i.e. a third doping level greater than the firstdoping level and less than the second doping level) and the drain accessregion 36″ has the first doping level.

As outlined above, according to embodiments of this presentation, the n+doping concentration in the ohmic contact regions 45, 46 can be between1×10{circumflex over ( )}19 and 9×10{circumflex over ( )}20cm{circumflex over ( )}-3. Such heavy doping of the ohmic contactregions reduces the ohmic contact resistance. According to embodimentsof this presentation, the dopant can be Si. Germanium (Ge) can also beused as an n-type dopant in GaN. According to embodiments of thispresentation, channel region 32 can be “unintentionally” doped (UID),effectively having a doping concentration of between 5×10{circumflexover ( )}15 and 5×10{circumflex over ( )}16 cm{circumflex over ( )}-3.The dopant can still be Si.

According to embodiments of this presentation, the portion of cappinglayer 36 referenced 36′ (regrowth regions marked “Regrowth A”) can havedoping concentrations of between 5×10{circumflex over ( )}15 and1×10{circumflex over ( )}19 cm{circumflex over ( )}-3. The dopant canstill be Si.

According to embodiments of this presentation, the portion of cappinglayer referenced as 36″ (the regrowth region marked “Regrowth C”) canhave a doping concentration of between 5×10{circumflex over ( )}15 and1×10{circumflex over ( )}19 cm{circumflex over ( )}-3, while being alsolower than the doping concentration in capping layer portion 36′, suchthat the resistance of capping layer 36/capping layer portion 36′ issmaller than the resistance of capping layer portion 36″, thus allowingto have a higher breakdown voltage in capping layer portion 36″ than incapping layer portion 36′. The dopant can still be Si.

FIG. 11 illustrates an embodiment of a HEMT 85 according to thispresentation, which is essentially identical to the HEMT 50 describedabove, except that the capping layer 36 between the gate 44 and thesource contact layer 45 forms a source access region 36′ having a givendoping and the capping layer 36 between the gate 44 and the draincontact layer 46 forms a drain access region 36″ having a differentdoping, as described above in relation to FIG. 10.

FIGS. 12A to 12H illustrate fabrication steps of a HEMT similar to HEMT80 of FIG. 10. The three first steps in FIGS. 12A, 12B, 12C areidentical to the three first steps detailed in FIGS. 8A, 8B, 8C.According to this embodiment of the presentation, however, the forming acapping layer mask 72 is different from the one described in relationwith FIG. 8D. According to this embodiment, the forming a capping layermask 72 comprises: initially forming a first half mask 72′ exposing onlya portion 38′ of surface 40 where access region 36′ of the capping layer36 is to be formed (FIG. 12D); and then forming access region 36′ onportion 38′ of surface 40 and removing half mask 72′ (FIG. 12E). Asillustrated, half mask 72′ can be arranged such that access region 36′overlaps slightly the source contact layer 45. According to thisembodiment of the presentation, the forming of a capping layer mask 72further comprises then forming a second half mask 72″ exposing only aportion 38″ of surface 40 where access region 36″ of the capping layer36 is to be formed (FIG. 12F), and then forming access region 36″ onportion 38″ of surface 40 and removing half mask 72″ (FIG. 12G). Asillustrated, half mask 72″ can be arranged such that access region 36″overlaps slightly drain contact layer 46. It is noted that removing halfmask 72″ causes the gate trench 42 to appear between access regions 36′and 36″. The gate dimension in this process depends on both the size andalignment of portions 72′, 72″ of mask 72.

The method can then comprise finalizing HEMT 80, by filling gate trench42 with gate conductor 44, eventually after forming a gate dielectric 60on the bottom and edges of the gate trench 42; as well as by formingsource conductor 48 and drain conductor 49 (FIG. 12H). As outlinedabove, gate conductor 44 can be part of a “T-shaped gate” as shown inFIG. 12G.

It is to be noted that the forming of the source and drain contacts 45,46, can alternatively take place after the forming of the capping layer46, as previously described in relation with FIG. 8.

FIGS. 13A to 13J illustrate fabrication steps of a HEMT similar to theHEMT 85 of FIG. 11. The three first steps in FIGS. 13A, 13B, 13C areidentical to the three first steps of FIGS. 9A, 9B, 9C as detailedabove. According to this embodiment of the presentation, however, afteretching away the gate barrier layer 76 using mask 72 and forming gatebarrier 52 (FIG. 13C), mask 72 is removed and a contact layer mask 70 isformed above gate barrier 52, exposing only portions 47 of the N-polarsurface 40 of channel 32 where the source and drain contact layers areto be formed (FIG. 13D). The method further comprises forming sourcecontact layer 45 and drain contact layer 46 on the exposed portions 47,and removing mask 70 (FIG. 13E). The method then comprises, consistentlywith FIG. 12, forming a first half mask 72′ exposing only a portion 38′of surface 40 where access region 36′ of the capping layer 36 is to beformed (FIG. 13F), and then forming access region 36′ on portion 38′ ofsurface 40 and removing half mask 72′ (FIG. 13G). As illustrated, halfmask 72′ can be arranged such that access region 36′ overlaps slightlysource contact layer 45 and contacts laterally gate barrier 52.According to this embodiment of the presentation, the method furthercomprises forming a second half mask 72″ exposing only a portion 38″ ofsurface 40 where access region 36″ of the capping layer 36 is to beformed (FIG. 13H), and then forming access region 36″ on portion 38″ ofsurface 40 and removing half mask 72″ (FIG. 13I). As illustrated, halfmask 72″ can be arranged such that access region 36″ overlaps slightlydrain contact layer 46 and contacts laterally gate barrier 52. It isnoted that removing half mask 72″ causes the gate trench 42 to appearbetween access regions 36′ and 36″, with gate barrier 52 on the bottomof gate trench 42. The method can then comprise finalizing HEMT 85, byfilling gate trench 42 with gate conductor 44, eventually after formingan optional gate dielectric 60 on the bottom and edges of the gatetrench 42; as well as by forming source conductor 48 and drain conductor49 (FIG. 13J). As outlined above, gate conductor 44 can be part of a“T-shaped gate” as shown in FIG. 13.

It is to be noted that the forming of the source and drain contacts 45,46, can alternatively take place after the forming of the capping layer46, as previously described in relation with FIG. 8.

FIG. 14 illustrates an embodiment of a HEMT 90 according to thispresentation, which can be structurally identical to the HEMT 30 of FIG.2, except that instead of having a drain contact layer 46 on surface 40,HEMT 90 comprises a drain contact layer 46′ formed on a portion 92 of atop surface of capping layer 36 arranged at a predetermined distance 94from the gate 44. The capping layer 36 of HEMT 90 can be longer on thedrain side than the capping layer 36 of HEMT 30; and the portion ofcapping layer 36 between gate 44 and drain contact layer 46′ forms adrain access region of HEMT 90. Consistently with the structure of HEMT30, a drain conductor 49 is formed on top of drain contact layer 46′.According to embodiments of this presentation, the drain access regionof HEMT 90 can allow electric fields to have higher breakdown voltagethan in the drain access region of HEMT 30. The drain access region ofHEMT 90 can thus allow higher breakdown voltage and reduce dc-RFdispersion as the device is self-passivated by the capping layer 36.According to an embodiment of this presentation, the portions of cappinglayer 36 on the side of the source and on the side of the drain can begrown in the same way as respectively portions 36′, 36″ as detailed inrelation with FIG. 10, so as to have a lower doping level of cappinglayer 36 on the side of the drain.

FIG. 15 illustrates an embodiment of a HEMT 96 according to thispresentation, which can be structurally identical to the HEMT 50 of FIG.3, except that instead of having a drain contact layer 46 on surface 40,HEMT 96 comprises a drain contact layer 46″ formed on a portion 98 of atop surface of capping layer 36 arranged at a predetermined distance 100from the gate 44. The capping layer 36 of HEMT 96 can be longer on thedrain side than the capping layer 36 of HEMT 50; and the portion ofcapping layer 36 between gate 44 and drain contact layer 46″ forms adrain access region of HEMT 96. According to embodiments of thispresentation, the drain access region of HEMT 96 can allow electricfields to have higher breakdown voltage than in the drain access regionof HEMT 50. The drain access region of HEMT 96 can thus allow higherbreakdown voltage and reduce dc-RF dispersion as the device isself-passivated by the capping layer 36. According to an embodiment ofthis presentation, the portions of capping layer 36 on the side of thesource and on the side of the drain can be grown in the same way asrespectively portions 36′, 36″ as detailed in relation with FIG. 10, soas to have a lower doping level of capping layer 36 on the side of thedrain.

FIGS. 16A to 16F illustrate steps of a fabrication method of the HEMT 90of FIG. 14. According to embodiments of this presentation, a first stepin FIG. 16A of this method is identical to the first step of the methodillustrated in FIG. 8A. The method further comprises forming on top ofsurface 40 a mask 102 masking portions 103, 104 of surface 40 that aredestined to receive source contact layer 45 and gate 44, and exposingportions 105, 106 of surface 40 that are destined to receive cappinglayer 36 on both sides (source and drain) of where gate 44 will stand(FIG. 16B). The method further comprises growing capping layer 36 onportions 105, 106 of surface 40, on both sides of where gate 44 willstand, and removing mask 102, thus exposing temporarily gate trench 42(FIG. 16C). The method further comprises growing a contacts mask 70above capping layer 36 on portions 105 of surface 40, above gate trench42, and above a section of capping layer 36 on portion 106 of surface 40so as to expose portion 92 of the top surface of capping layer 36 thatis on portion 106 of surface 40 (FIG. 16D).

The method further comprises growing simultaneously source contact layer45 on portion 103 of surface 40 and drain contact layer 46′ on portion92 of the top surface of capping layer 36, on portion 106 of surface 40,then removing mask 70 (FIG. 16E). Removing mask 70 exposes gate trench42. The method can then comprise finalizing HEMT 90, by filling gatetrench 42 with gate conductor 44, eventually after forming an optionalgate dielectric 60 on the bottom and edges of the gate trench 42; aswell as by forming source conductor 48 and drain conductor 49 (FIG.16F). As outlined above, gate conductor 44 can be part of a “T-shapedgate” as shown in FIG. 16F.

FIGS. 17A to 17H illustrate fabrication steps of a HEMT similar to theHEMT 96 of FIG. 15. The three first steps, illustrated in FIGS. 17A,17B, 17C, are identical to the three first steps illustrated in FIGS.9A, 9B, 9C as detailed above. According to this embodiment of thepresentation, however, after etching away the gate barrier layer 76using mask 72 and forming gate barrier 52 (FIG. 17C), mask 72 is notremoved and mask 110 is formed, additionally masking a portion 103 ofsurface 40 destined to receive source contact layer 45 and exposingportions 105, 106 of surface 40 destined to receive capping layer 36 onboth sides (source, drain) of gate barrier 52 (FIG. 17D). The methodfurther comprises growing capping layer 36 on portions 105, 106 ofsurface 40 on both sides of gate barrier 52, and removing masks 72 and110 (FIG. 17E). The method further comprises growing a contacts mask 70above capping layer 36 on portion 105 of surface 40, above gate barrier52, and above a section of capping layer 36 on portion 106 of surface 40so as to expose portion 92 of the top surface of capping layer 36 onportion 106 of surface 40 (FIG. 17F).

The method further comprises growing simultaneously source contact layer45 on portion 103 of surface 40 and drain contact layer 46′ on portion92 of the top surface of capping layer 36 on portion 106 of surface 40,then removing mask 70 (FIG. 17G). Removing mask 70 exposes gate barrier52 in gate trench 42. The method can then comprise finalizing HEMT 96,by filling gate trench 42 with gate conductor 44, eventually afterforming an optional gate dielectric 60 on the bottom and edges of thegate trench 42; as well as by forming source conductor 48 and drainconductor 49 (FIG. 17H). As outlined above, gate conductor 44 can bepart of a “T-shaped gate” as shown in FIG. 17H.

FIG. 18 illustrates an embodiment of a HEMT 115 according to thispresentation, which is essentially identical to HEMT 30 of FIG. 2,except that instead of having a monolithic channel layer 32, HEMT 115comprises a graded channel layer 118 (Specifically: a compositionallygraded channel layer 118, whose composition (e.g., Al mole fraction inAlGaN) varies along its thickness). A graded channel layer increases thevertical thickness of the two-dimensional electron gas and moves thecentroid of charge away from the heterostructure interface. This allowsthe HEMT transconductance to remain high at broader range of draincurrents, which increases device linearity and high-frequency operatingrange. A graded channel is for example achieved by making a gradualtransition from the AlGaN barrier layer to the GaN channel duringepitaxial growth.

FIG. 19 illustrates an embodiment of a HEMT 120 according to thispresentation, which is essentially identical to HEMT 50 of FIG. 3,except that instead of having a monolithic channel layer 32, HEMT 115comprises a graded channel layer 118 such as described in FIG. 18. Asfor FIG. 18, a graded channel layer increases the vertical thickness ofthe two-dimensional electron gas and moves the centroid of charge awayfrom the heterostructure interface. This allows the HEMTtransconductance to remain high at broader range of drain currents,which increases device linearity and high-frequency operating range. Agraded channel is achieved by making a gradual transition from the AlGaNbarrier layer to the GaN channel during epitaxial growth.

FIGS. 20A to 20F illustrate fabrication steps of the HEMT 115 of FIG.18. According to embodiments of this presentation, the method offabrication of HEMT 115 can be identical to the method of fabrication ofHEMT 30, except that at the end of the first step (FIG. 20A), a gradedchannel layer 118 is grown instead of channel layer 32. It is noted thatHEMT 115, as shown in FIG. 18, does not comprise the optional gatedielectric 60 shown in FIG. 20F.

FIGS. 21A to 21E illustrate fabrication steps of the HEMT 120 of FIG.19. According to embodiments of this presentation, the method offabrication of HEMT 120 can be identical to the method of fabrication ofHEMT 50, except that at the end of the first step (FIG. 21A), a gradedchannel layer 118 is grown instead of channel layer 32. It is noted thatHEMT 120, as shown in FIG. 19, does not comprise the optional gatedielectric 60 shown in FIG. 21E.

According to embodiments of this presentation, in the above-describedmethods of fabrication the regions not intended to see regrowth can bemasked with SiO2 and regrowth can be performed by molecular beamepitaxy, before removing the SiO2 masks. Alternate masks, growthtechniques, and process flows can be used as well (for example SiN masksor metal-organic chemical vapor phase deposition growth). The devicesdiscussed here can use SiN gate dielectric under the gate metal, andoptionally over the final regrowth cap layers as additional surfacepassivation, but alternate surface passivation or treatments may also beused.

FIG. 22 illustrates HEMT 90 of FIG. 14 and shows locations of interestused in FIGS. 23A, 23B and 23C.

FIG. 23A illustrates energy band diagrams under the source; FIG. 23Billustrates energy band diagrams under the gate and FIG. 23C illustratesenergy band diagrams under the drain of HEMT 90, at the locationsindicated in FIG. 22. As shown in FIGS. 23A-C, the asymmetric structureof HEMT 90 allows having low losses in the source, while selfpassivating the high-field drain access region, without compromisingdevice breakdown. The asymmetric structure is achieved by offsetting thegate towards the source, which reduces the gate-source distance and thesource access resistance, as a result. The source access resistance is aparasitic element that degrades HEMT performance, specifically thetransconductance, the frequency figures of merit, the drain current, theoutput power, and the device efficiency. Reducing the source accessresistance by offsetting the gate to the source improves each figure ofmerit. Increasing the gate-drain spacing improves the device breakdownvoltage, the operating voltage, and the device output power.

The foregoing Detailed Description of exemplary and preferredembodiments is presented for purposes of illustration and disclosure inaccordance with the requirements of the law. It is not intended to beexhaustive nor to limit the invention to the precise form(s) described,but only to enable others skilled in the art to understand how theinvention may be suited for a particular use or implementation. Thepossibility of modifications and variations will be apparent topractitioners skilled in the art. No limitation is intended by thedescription of exemplary embodiments which may have included tolerances,feature dimensions, specific operating conditions, engineeringspecifications, or the like, and which may vary between implementationsor with changes to the state of the art, and no limitation should beimplied therefrom.

Applicant has made this disclosure with respect to the current state ofthe art, but also contemplates advancements and that adaptations in thefuture may take into consideration of those advancements, namely inaccordance with the then current state of the art. It is intended thatthe scope of the invention be defined by the Claims as written andequivalents as applicable. Reference to a claim element in the singularis not intended to mean “one and only one” unless explicitly so stated.Moreover, no element, component, nor method or process step in thisdisclosure is intended to be dedicated to the public regardless ofwhether the element, component, or step is explicitly recited in theClaims. No claim element herein is to be construed under the provisionsof 35 U.S.C. Sec. 112, sixth paragraph, unless the element is expresslyrecited using the phrase “means for . . . .” and no method or processstep herein is to be construed under those provisions unless the step,or steps, are expressly recited using the phrase “comprising the step(s)of . . . .”

1. A HEMT comprising a channel layer of a first III-Nitridesemiconductor material, grown on a N-polar surface of a back barrierlayer of a second III-Nitride semiconductor material; the secondIII-Nitride semiconductor material having a larger band gap than thefirst III-Nitride semiconductor material, such that a positively chargedpolarization interface and two-dimensional electron gas is obtained inthe channel layer; a passivation, capping layer, of said firstIII-Nitride semiconductor material, formed on top of and in contact witha first portion of a N-polar surface of said channel layer; a gatetrench traversing the passivation, capping layer, and ending at saidN-polar surface of said channel layer; and a gate conductor filling saidgate trench.
 2. The HEMT of claim 1, comprising a thin layer of a thirdIII-Nitride semiconductor material in said gate trench between said gateconductor and said N-polar surface of said channel layer.
 3. The HEMT ofclaim 1, wherein said passivation, capping layer, is a layer grown onsaid first portion of said N-polar surface of said channel layer.
 4. TheHEMT of claim 1, wherein said first III-Nitride semiconductor materialis GaN and said second III-Nitride semiconductor material is AlGaN. 5.The HEMT of claim 2, wherein said third III-Nitride semiconductormaterial is one of AlN, InAlN, AlGaN and InAlGaN.
 6. The HEMT of claim1, comprising a source contact layer and a drain contact layer of afourth Ill-Nitride semiconductor, formed on a second portion of saidN-polar surface of said channel layer on opposite sides of said gatetrench.
 7. The HEMT of claim 6, wherein said channel layer has a firstdoping level and said source and drain contact layers have a seconddoping level larger than the first doping level, wherein: a sourceaccess region of said passivation, capping layer, arranged between thesource contact layer and the gate trench, has a third doping levelcomprised between the first and second doping levels; and a drain accessregion of said passivation, capping layer, arranged between the draincontact layer and the gate trench, has the first doping level.
 8. TheHEMT of claim 6, wherein said source contact layer and said draincontact layer are layers grown on said second portion of said N-polarsurface of said channel layer.
 9. The HEMT of claim 6, comprising asource conductor and a drain conductor in contact with respectively saidsource contact layer and said drain contact layer.
 10. The HEMT of claim6, wherein said fourth II-Nitride semiconductor material is n+ doped GaNor n+ doped InGaN.
 11. The HEMT of claim 1, comprising: a source contactlayer of a fourth III-Nitride semiconductor, formed on a second portionof said N-polar surface of said channel layer on a first side of saidgate trench; and a drain contact layer of said fourth III-Nitridesemiconductor, formed on a portion of a top surface of said passivation,capping layer, on a second side of said gate trench opposite said firstside of said gate trench.
 12. The HEMT of claim 11, wherein said channellayer has a first doping level and said source and drain contact layershave a second doping level larger than the first doping level, wherein:a source access region of said passivation, capping layer, arrangedbetween the source contact layer and the gate trench, has a third dopinglevel comprised between the first and second doping levels; and a drainaccess region of said passivation, capping layer, arranged between underthe drain contact layer and the gate trench, has the first doping level.13. The HEMT of claim 11, wherein said source contact layer and saiddrain contact layer are layers grown respectively on said second portionof said N-polar surface of said channel layer and on said portion of atop surface of said capping layer.
 14. The HEMT of claim 11, comprisinga source conductor and a drain conductor in contact with respectivelysaid source contact layer and said drain contact layer.
 15. The HEMT ofclaim 6, wherein said fourth III-Nitride semiconductor material is n+doped GaN or n+ doped InGaN.
 16. The HEMT of claim 1, wherein a gateinsulator layer lines the side and bottom of said gate conductor in saidtrench.